In-System Silicon Validation and Debug: Part 2

By Miron Abramovici and Paul Bradley, Dafca
October 02, 2007 -- edadesignline.com
   
This is the second in a series of three articles on silicon validation, introducing a new approach and some basic applications. Part 1 presented the silicon validation problem and the requirements of an effective and scalable solution. Part 3 will analyze the silicon results of four devices designed with the approach described here. You can read Part 1 here

The new approach

Pre-silicon, ClearBlue Instrumentation Studio from Dafca guides the insertion of reconfigurable instruments into the RTL of a design, and generates an instrumented SoC model that is processed by standard synthesis-based design flows. The instrumentation creates a validation infrastructure platform that is dynamically configured and operated post-silicon by the ClearBlue Silicon Validation Studio analysis tool. Dynamic in-system configuration " accomplished without stopping the clock or impacting performance " enables continuous reuse of the instrumentation for a variety of applications. Silicon Validation Studio configures and controls the instruments through a JTAG Test Access Port via a parallel port cable or an Ethernet connection, so no extra pins or special libraries are required.

The instrumentation and the post-silicon applications can also be used pre-silicon with a simulator, emulator, or FPGA prototype, all with the same user interface. This allows the user to verify the instrumentation and to create a suite of validation, data acquisition, performance monitoring, stress testing, and debug scripts that can be automatically applied when the ASIC/SoC is available in the lab.

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