Ensuring Power Designing Works at 65nm

By LC Lu, TSMC and George Kuo, Cadence Design Systems
October 22, 2007 -- edadesignline.com

When designers jump from the 90-nanometer (nm) to 65nm process nodes, many factors conspire to make things more complicated. For instance, at 65nm, designers can fit a lot more functionality onto a chip, which draws considerably more power " unless the designer knows how to optimize for power reduction. TSMC has already optimized its technology for low power design. The 65nm process uses new gate-oxide material, strain engineering, and low-K interconnect dielectric. Nevertheless, at that feature size, dynamic and leakage power issues remain. This means techniques for mitigating power consumption must come from the design side. The earlier these low power design techniques are employed, the greater the return in power savings.

To accommodate foundry customers' 65nm designs, it is in everyone's best interest to fully leverage TSMC processes with compatible, power-saving EDA tools. TSMC already brings to bear low-power methodologies and IP aimed at reducing dynamic, active, and standby power leakage. All of these low-power methodologies require fully automated EDA support.

However, a fully optimized low power methodology requires more than just process support. It also requires that design tools in the methodology communicate low power design intent in a single, standard format. The Si2 Common Power Format (CPF), the first low-power EDA format embraced by TSMC for 65-nm low power design, enables this capability.

Ultimately, low power designs employ a variety of power reduction techniques such as power gating, multiple-voltage domains and dynamic voltage scaling. Because there are so many concurrent variables in designing with multiple techniques, TSMC has taken a phased approach to ensuring that automation of these techniques results in verifiable improvements to 65nm designs. This article describes an early program to validate the Common Power Format for use with TSMC technology.

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