Using Serial RapidIO for FPGA co-processing

By Navneet Rao, Xilinx
November 08, 2007 -- dspdesignline.com

Today's ever increasing demand for high-speed communication and super-fast computing in support of "triple-play" applications is creating new challenges for system developers, algorithm developers and hardware engineers alike who need to draw together a multitude of standards, components and networking equipment. At the same time, developers need to keep pace with increasing demands for performance while keeping costs low. These feats can be accomplished by leveraging Serial RapidIO-enabled FPGAs as DSP co-processors.

Because triple-play applications unite voice, video and data, development and system optimization strategies must be parameterized using newer algorithms. Specific challenges that developers need to address include building scalable and extensible architectures, supporting distributed processing, using standards-based design, and optimizing for performance and cost.

A closer look at these challenges reveals two themes: Connectivity—which is essentially "fast" data movement across devices, boards and systems—and Computing power—i.e., the individual processing resources that are available in the devices, boards and systems—address the needs of the application.

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