Leveraging system models for RTL functional verification

Jerome Bortolami, Calypto Design Systems
(12/03/2007 9:00 AM EST), EE Times

Sequential logic equivalence checking provides an edge

Register transfer level (RTL) verification remains the bottleneck in digital hardware design. Industry surveys show that functional verification accounts for 70 percent of the total design effort. Yet, despite the emphasis on verification, more than 60 percent of all design tapeouts require a respin. The predominant cause is logic or functional flaws, defects that could have been caught by functional verification. Clearly, improved verification techniques are needed.

Design teams commonly use system models for verification. System models have advantages over RTL for verification: namely, ease of development and run-time performance. The challenge is bridging the gap between system-level verification and creating functionally correct RTL. A methodology known as sequential logic equivalence checking has the ability to bridge this gap by formally verifying RTL implementations against a specification written in C/C++ or SystemC.

This case study describes the system-level to RTL design and verification flow of a commercial graphics processing chip. In this flow, system models were developed to validate the arithmetic computation of video instructions and were then used to verify the RTL implementation using sequential logic equivalence checking.

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