Comparing IP integration approaches for FPGA implementation

Avoiding the fixed routing and timetable of a standard bus can open up new avenues for design and restore a bit of glamour and creativity to an otherwise mundane project.

By Richard Venia, Altera
(02/20/08, 12:29:00 PM EST) -- Programmable Logic DesignLine

Since the early days of computers and telephony, interconnection networks have been a critical part of electrical engineering. This has become even more critical in the era of very large-scale integration (VLSI) circuitry because of the drive characteristics of MOS transistors combined with the relatively high capacitance of on-chip interconnects.

The interconnection networks used to connect functional units within a chip can have a significant, even a dominating, effect on the performance of a device. Buses, although the simplest form of interconnect, are a poor choice from a density or power standpoint because the power and space required to drive them at maximum speed grow exponentially with the capacitance of the bus. Furthermore, multi-point connection networks are a poor choice as the entire length of the bus must be driven even when only a single "conversation" may be going on at a time, or where the communication is between direct neighbors. A crossbar is an optimal solution, up to a maximum size determined by the underlying device and wiring technology. In general, the optimal solution to multi-party communication is a network built out of crossbars.

Status Quo
On-chip buses today are a simple and straightforward outgrowth of the system-wide buses used in computer systems. Although there is obvious proof that such buses are functional, they were typically designed for the commercial and technical limitations of their day, when wires were cheap, circuits were expensive, and interconnect was faster than logic.

Today this is not the case. Modern large-scale integrated circuits (ICs) are routinely speed-limited by the interconnect, not by the logic. The evidence is everywhere in devices with multiple clock domains and/or exotic wave-propagation techniques. Logic gates are now plentiful, when considering "Moore's Law" that historically has delivered more gate density than most engineers knew what to do with. This predicament has turned circuit and system design on its head: logic and interconnects are inexpensive and conserving wires is counter-productive.

Buses led to the development of bus standards, but bus standards do not solve the bigger problems of system architecture and data flow Bus standards, like many laws, policies, and regulations, have a way of outliving their usefulness. Bus standards are intolerant of changes in signaling, protocol, bandwidth, or usage model. Buses are, by nature, slow to change and quick to stifle the unexpected. It's been said that they deter innovation and impede originality. Still they remain steadfast beacons of standardization in a sea of ever-present change and progress.

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