Strategies for minimizing Xilinx implementation tool runtimes

By Philippe Garrault, Xilinx
March 24, 2008 -- pldesignline.com

Overview

FPGAs have evolved tremendously in terms of capacity and performance, and they can now be used to implement more core functionality. From an algorithmic perspective, extra features and density often translate into exponential complexity. If left unchecked, the implications of this complexity on place-and-route runtimes could become a significant impediment to a designer's productivity. At the same time, from a user's perspective, software runtimes must be kept reasonably "fast." Whether it is during logic creation, logic verification, design constraints closure, or in-system debugging, designers need the ability to perform multiple design iterations per day through the place-and-route tool to move the project toward completion at an acceptable pace.

This document provides tips, techniques, and new options for controlling runtime in the Xilinx ISE Design Suite 10.1 release. The first section places the FPGA design cycle in the broader context of system development. It highlights the steps that typically require fast implementation runtime and – for each step – what the design properties are. The second section introduces the ISE 10.1 algorithmic improvements and provides a description of the new flows and options available for controlling software runtime. The third section lists a set of strategies that may be used at each stage in the development cycle to improve runtime.

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