Bridging the Gap Between Silicon and Software Validation

By Paul Bradley, DAFCA, Inc
June 06, 2008 -- edadesignline.com
  
Post-silicon SoC "whole system" validation solutions have lagged behind the increasing complexity of low power schemes, multi-core architectures, complex clock domains and sub 90 nm manufacturing. This is a bad news/good news story. The bad news is that teams developing massive and complex SoCs already realize that they cannot ignore their plans for the post-silicon phase, and that legacy patchwork solutions are no longer sufficient. The good news is that the new paradigms and methodologies employed in the pre-silicon verification space can be leveraged in post-silicon validation. Indeed, the blueprint for abstraction, visibility, messaging, and assertion checking already exists.

Today, complex SOC and ASIC designs require advanced validation and debug solutions that bridge the gap, not just between pre-silicon and post-silicon, but perhaps more importantly, between embedded software and hardware systems.

The need for visibility and control between software and hardware systems is not new. However, the lack of visibility and control has become an acute problem, especially as SoC hardware functions and embedded software systems have grown more complex. The challenge is compounded by multi-core designs composed of heterogeneous third-party processors, buses, switches, and peripherals, where reduced on-chip visibility of key functions and inter-block communications is the current norm. The visibility problem is not limited to complex hardware interactions, but extends to embedded software systems operating on the hardware.

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