Surveying the hardware-assisted verification landscape

By Lauro Rizzatti, EVE-USA    
edadesignline.com (July 30, 2008)

This year's Design Automation Conference (DAC) served as an ideal setting for checking in on the ongoing verification requirements of today's design teams and test out a few theories on hardware-assisted verification. Over the course of the four-day conference in June, the team staffing the EVE booth asked a series of questions to a sampling of DAC attendees and received some surprising and some not so surprising answers.

We met with system architects, designers, verification and validation engineers, managers and electronic design automation (EDA) tool support managers, all of whom dropped in to give us an update and check in on what we're doing. Most hold engineering staff positions and all of them graciously consented to answering a short usage survey. Additionally, most of the attendees we surveyed were designing consumer and wireless products, and the concentration was from the United States and Asia.

When asked which language they use for application specific integrated circuit (ASIC) design, 59% said Verilog, followed in order by SystemVerilog (26%), VHDL (23%) and SystemC (12%). For testbench design, Verilog continues to dominate with 38%, followed by SystemVerilog/Verification Methodology Manual (VMM) (30%), VHDL (13%), SystemC (11%) and Specman (8%), with Vera (5%) trailing behind. This indicates that there is a clear migration from traditional hardware verification languages (Specman and Vera) to SystemVerilog.

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