Antifuse memory IP fuels low-power designs

Update: Synopsys Expands DesignWare IP Portfolio with Acquisition of Sidense Corporation (Oct. 17, 2017)

Jim Lipman, Sidense
EE Times (08/01/2008 6:00 PM EDT)

Embedded nonvolatile memory is becoming more prevalent in a wide range of chips, particularly for power-sensitive applications. Memory IP for such apps requires the design of both the basic memory bit and the memory macro architecture to minimize power demands. An appropriate one-time programmable (OTP) memory macro can meet nonvolatile-memory requirements while offering low-power operation.

Many applications that require nonvolatile memory (NVM) do not need hundreds or thousands of rewrite cycles. Code storage, calibration tables, setup parameters and the like seldom, if ever, need changing once programmed. For cases in which occasional change is required, an appropriate memory management algorithm can skip over outdated information and use previously empty memory to hold the updates. Such management lets a low-cost and secure antifuse-based OTP memory serve as a design's embedded memory just as effectively as a rewritable NVM.

The cost advantages of antifuse-based OTP memory stem from the cell size and process complexity. The antifuse memory's design can be as small as one transistor using technology such as Sidense's 1T-Fuse memory IP. The result is a memory cell area that is much smaller than floating-gate multi-time-programmable (MTP) memories. The small bit cell size results in a smaller memory array footprint, which in turn reduces the area-related cost of the die.

The reliability of antifuse-based OTP stems from the simplicity of its operation. When programmed, the antifuse is a permanent and desired short circuit that cannot be accidentally formed under normal memory read operations. Floating-gate NVM, though rewritable, can wear out because of the need to tunnel electrons on and off the gate during programming and erasure. The tunneling operation will eventually break down the oxide layer isolating the floating gate, creating a permanent, undesired short-circuit in the memory cell.

The simplicity of operation also makes OTP memory an inherently lower-power design than other NVMs. By transistor count alone, for example, antifuse-based memory would be expected to draw less power. In addition, its compact cell size means that arrays are physically smaller. That lowers the capacitance of the bit and word lines, reducing both precharge and switching power consumption.

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