Virtual prototypes speed wireless development

Update: ARM to Offer Cycle-Accurate Virtual Prototyping for Complex SoCs Through an Asset Acquisition from Carbon Design Systems (October 20, 2015)

Bill Neifert, CTO and a co-founder, Carbon Design Systems
EE Times (10/27/2008 12:01 AM EDT)

More than one billion wireless devices are sold every year. This enormous volume, in combination with the hardware and software complexity of the devices, has given rise to an uncountable number of technical advances. Seemingly small changes of pennies per unit in manufacturing costs, or a slip in the delivery schedule, can add up to substantial dollar amounts when combined with the sheer volume of devices to be manufactured.

One technology gaining widespread acceptance within the wireless design community is the use of virtual prototypes throughout the design cycle. Wireless engineers are leveraging virtual prototypes of their system-on-chip designs to improve product quality and speed time to market. A virtual prototype can be an indispensable tool for performing early architectural analysis for throughput and power tradeoffs. Firmware developers can use virtual prototypes to develop and debug their software in advance of real silicon. In addition, virtual prototypes can be used to optimize the throughput of designs that have been built already.

Moving beyond spreadsheets

Until recently, architectural exploration was relatively ad hoc. Back-of-the-envelope calculations, combined with a few spreadsheets and years of design expertise, comprised the entire architectural flow for many chips and systems. This methodology is elegant in its simplicity but fails to deliver the architectural certainty required by most wireless apps.

A poorly designed architecture can present itself in many ways. The most visible evidence is that it doesn't meet its performance targets. Underperforming chips can sometimes be revived by creative firmware engineers and extra months in the lab. More often than not, slow chips are relegated to the trash heap.

The more common, and far less obvious, architectural failing is overdesign. The worst-case conditions of various spreadsheet components are added together--including those that would never occur together in the real world--and the architect generates a design exceeding specifications.

Overdesigned architectures have hidden costs associated with them. Expensive, high-speed memory may be used in cases where less expensive, slower components might have sufficed. The main processor clock running at 400 MHz might have run fine at 300 MHz instead. The ultimate price for an overdesigned architecture is typically seen in an end product that costs more and has a shorter battery life than competitive products. The problems resulting from overdesign may not be as obvious as those from underdesign, but the end result is not much different.

Virtual prototypes remove the guesswork from architectural decisions because the architect can explore multiple design scenarios and get an in-depth understanding of the real-world impacts of various design decisions and intellectual property (IP) selections. Analysis tools can be used to display such critical items as throughput, loading and latency. These results can be examined on a cycle-by-cycle basis and directly correlated with various hardware and software components. The data available from a virtual prototype can enable an architect to confidently make big decisions, such as which IP block to select, as well as seemingly smaller ones, such as what arbitration scheme to employ.

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