PRODUCT HOW-TO: Taking the delay out of your multicore design's intra-chip interconnections

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

By Steve Leibson, Tensilica
Embedded.com (01/07/09, 02:43:00 PM EST)

Today's SOC designers readily accept the idea of using multiple processor cores in their complex systems to achieve design goals. Unfortunately, a 40-year history of processor-based system design has made the main processor bus the sole data highway into and out of most processor cores. The widespread use of processor cores in SOC designs and the heavy reliance on the processors main buses for primary on-chip interconnect, produces SOC architectures based on bus hierarchies like the one shown in Figure 1 below.


Figure 1: SoCs with multiple processors often employ bus hierarchies

Because processors interact with other types of bus masters " including other processors and DMA controllers " main processor buses feature sophisticated transaction protocols and arbitration mechanisms that enable such design complexity.

These protocols and arbitration mechanisms usually require multi-cycle bus transactions that can slow system performance. As more processors are designed into a chip to perform more processing, the hierarchy of buses architecture shown in Figure 1 becomes increasingly inefficient, because more processors are using inefficient bus arbitration and transaction protocols to gain access to and to use relatively limited bus interconnect resources.

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