Power-aware FPGA design (Part 2)

Analyzing differences in area, timing, and power attributes for different implementations of the same basic design reveals that considering simple, single-cycle power numbers is misleading and even erroneous.

By Hichem Belhadj, Vishal Aggrawal, Ajay Pradhan, and Amal Zerrouki, Actel
pldesignline.com (February 11, 2009)

Part 1
– Abstract
– Introduction
– FPGA Power Components and System Profile
– Fighting Static Power
– Fighting Dynamic Power

Part 2
– Fighting Dynamic Power (continued)

Part 3
– Fighting Dynamic Power (continued)
– Proposed Power Reduction Methodology
– Conclusions
– References

Other techniques to reduce RAM power
There are more opportunities to reduce wasted power; in particular, when cascading multiple blocks to build a large RAM, or when the data and/or the address bits are not changing systematically every clock cycle. The following sections address these...

RAM Cascading
FPGAs offer several embedded RAM blocks with unique sizes but variable aspect ratios. This feature opens the door for different cascading schemes. Fig 9 is an illustration of two alternatives that have different timing and power attributes.

9. Potential embedded RAM cascading schemes for 4Kx4 RAM.

In one case, all the RAM blocks toggle at each clock cycle as their outputs are concatenated to build the output. In the second case, only one RAM block is active at a time. However, there is overhead logic that not only could consume extra power, but also definitely affects timing. Users should check whether the address-generation logic addresses one RAM a large number of times before moving on to another one. If the address locality is guaranteed, then cascading schemes where only one RAM is active at a time are viable. The next section on gating the clock and enable signals includes some actual silicon power results.

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Power-aware FPGA design (Part 2)

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