Behavioral Design Drives Low-Power Silicon

By Brett Cline, Mike Meredith, Forte Design Systems
edadesignline.com (February 16, 2009)

Hardware designers adopt high level synthesis (HLS) for productivity benefits, and need the quality of results (QoR) to match or exceed what they can achieve with hand-constructed register transfer level (RTL) code. Historically, the most interesting QoR metrics have been limited mostly to circuit performance and chip area. As power consumption has risen in prominence as a dominant design criteria, it has also become a QoR metric of interest to HLS users.

Users of the new generation of high-level synthesis tools find that HLS can be used effectively to improve power consumption along with the other measures of circuit quality. Some of these improvements come from optimizations made by the HLS tool itself. Additional power reduction is achieved as a result of the inherent improvement HLS brings to the design flow, giving the designer the flexibility to easily experiment and identify the solution that consumes the least power.

High-level designers use a broad range of techniques to improve the overall power profile of their designs, including: power reduction by optimizing system architecture; micro-architecture exploration in the power dimension; high-level coding styles to reduce power; RTL coding styles for power optimization; and power optimizations made by HLS.

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