How to reduce power consumption in CPLD designs with power supply cycling

Power supply cycling offers designers a viable means to achieve the desired features as well as low power consumption in their CPLD designs.

By Gordon Hands, Lattice Semiconductor
pldesignline.com (March 11, 2009)

It is increasingly common for Complex Programmable Logic Devices (CPLDs) to be used in systems with stringent power budgets. Examples include smart phones, handheld instrumentation, video recording equipment, and navigation devices. Although a number of "zero power" CPLDs exist with standby power measured in microamps, these devices often don't have the features required for a particular design. In these cases, power supply cycling offers designers a viable means to achieve the desired features as well as low power consumption.

The duty cycle approach to power consumption reduction relies on the fact that for much of the time equipment is operational there is often little processing required by the CPLD. For example, the CPLD may be scanning a key pad to see if a key press has occurred, or is waiting for some communication on a serial interface.

CPLDs, like all integrated circuits, consume some power associated with device bias and leakage, regardless of activity. This power is often referred to as static current. CPLDs also consume power as a result of signals switching inside the device. This power is often referred to as dynamic power.

The amount of energy consumed as dynamic power is proportional to the amount of processing undertaken. Thus, achieving an operation in 0.1 seconds at 100 MHz consumes approximately the same amount of energy (in terms of dynamic power) as achieving the same operation in ten seconds at 1 MHz.

These characteristics of dynamic and static power can be used to minimize the overall power consumption of a design by compressing required activity into a small time period and turning off the CPLD during periods of inactivity.

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