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Inside Ceva's high-performance XC core for 4G handsets, infrastructure
By BDTI
April 14, 2009  In February CEVA announced a new family of high-performance licensable DSP cores, the CEVA-XC family. The cores target 4G cellular applications, including LTE and WiMax, and are intended for use not just in handsets (as with previous CEVA cores) but also in infrastructure hardware.The CEVA-XC is an offshoot of the CEVA-X architecture (the "C" stands for communications), but the new core family is much more powerful than its predecessors. The highest-performance version supports, for example, up to 64 parallel multiply-accumulate (MAC) computations per cycle, compared to four for the CEVA-X1641. CEVA has not announced specific clock speeds, but says that it expects CEVA-XC to easily reach 500 MHz in a 65-nm process with a fully synthesizable design. Silicon area has not been disclosed. (Click to enlarge) Figure 1: Block diagram for CEVA-XC. (Figure courtesy of CEVA.) As shown in Figure 1, the core includes a general computation unit for general DSP and control operations, and either one, two, or four "vector communication units". Each vector unit includes a 256-bit SIMD engine that includes16-bit MAC, arithmetic, and logic units.
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