Rapid debug of serial buses in FPGAs

By Joel Woodward
pldesignline.com (June 30, 2009)

Sub-megabit serial buses can be found in most embedded FPGA designs. Multi-gigabit serial bus inclusion in FPGAs is gaining traction. Serial buses' ease-of-implementation, low cost, and ties with legacy design blocks make them ideal for a wide variety of applications across a broad number of industries. Low-speed serial buses remain prevalent in computer, semiconductor, aero/defense, communications, consumer automotive, medical, test and measurement industries.

Serial buses such as I2C, SPI, CAN, LIN, and RS-232 are often key points for debugging designs with FPGAs which higher speed serial buses quickly pass data from chip to chip. Historically, capturing and decoding the information required significant manual effort if using an oscilloscope or the purchase of custom tools. Oscilloscope vendors now incorporate significant application technology that simplifies debug of low-speed serial buses.

The reprogrammable nature of FPGAs makes iterative debug effective and it's often advantageous to move quickly from simulation to prototyping. Digital oscilloscopes (DSOs) and mixed signal oscilloscopes (MSOs) naturally make good tools to probe low-speed serial interfaces. Offering 16 or more digital channels in addition to scope channels, MSOs have the added advantage of allowing for debug of internal parallel data buses, state machines, control signals, and parallel I/O interfaces that are problematic for DSOs' limited nature of scope channels only.

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