PRODUCT HOW-TO: Debugging hardware designs with an FPGA-based emulation tool

By Ludovic Larzul, EVE
industrialcontroldesignline.com (August 24, 2009)

Creating a hardware emulation system is no easy task. At a minimum, each generation of emulation system has to accommodate a growing number of logic gates, memory and DSP blocks to allow ASIC and ASSP SoC designers to debug their extremely complex devices before sending them off to the foundry for production. Emulation systems must also be easy to program, reliable and affordable.

Today's SoCs are exceedingly complex pieces of silicon. They contain one or more processors that will execute software. The software code they run is every bit as important a part of the final system as the silicon itself.

The software and the silicon have to act as a seamless solution; if there's a problem, it might be the software, or it might be the silicon. Designers can only do so much software testing on a development host. No reasonable host development system can reflect the true parallelism of the target SoC.

You can really only test out such issues as synchronization, data integrity and resource contention in situ, and that's far too late to identify problems. Simulation isn't a viable solution; it's simply too slow to allow the execution of any realistic code.

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