Lowering test costs in the nanometer era

By Sanjiv Taneja, Vice President, Encounter Test, Cadence Design Systems
edadesignline.com (December 15, 2009)

Design for test (DFT) has not drawn the kind of attention that design for manufacturability (DFM) has received in recent years, but test is becoming significantly more difficult and expensive at nanometer process nodes. Test costs are escalating, adding to overall product costs, and the potential for yield loss due to test-related issues is rising. What's needed is a renewed focus on DFT with a more holistic view of the economics of test than we've had in the past.

Conventionally, test costs are evaluated in terms of capital costs and operating costs. The evaluation starts with the cost of the ATE equipment and considers what it costs to operate the equipment for a given period of time. The focus then shifts to optimizing throughput so as to minimize the time that any one IC spends on the tester. To do so, test engineers seek to provide maximum test coverage within a minimum data volume so results can be provided in the shortest possible time.

While these considerations are still important, the notion of "test cost" needs to take a much broader view given the advances in nanometer process technology, the increasing role of analog/mixed-signal circuitry, and the drive for low-power design. Cost evaluations must consider power, design/test integration, analog/mixed-signal test, the cost of escaped defects, and product yield learning. EDA technology needs to provide tangible ways of reducing costs in each of these areas.

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