EDA leaders trade places

The report provides an industry overview as well. This year, Gartner Dataquest notes that license-model changes are continuing to dampen revenues for Cadence Design Systems and Synopsys. Mixed-language, Verilog/VHDL simulation came on strong in 2001, the survey reports, as did formal analysis, although the latter market is hobbled by the lack of a stan dard assertion language.

Looking at individual markets, the report notes that Novas jumped to the No. 1 position in RTL design, led by Summit Design in 1999. Cadence displaced Mentor Graphics as the leader in VHDL simulation, but Mentor grabbed the No. 1 spot in the new mixed-language simulation arena.

Avanti's 1999 lead in formal verification collapsed to a weak No. 3 position, following Synopsys and a resurgent Verplex. Cadence made no progress in RTL synthesis, with just 10 percent market share compared with Synopsys' 87 percent. Synplicity leapfrogged both Synopsys and Mentor to grab the No. 1 position in FPGA synthesis.

Mentor has taken over hardware/software co-verification with a 90 percent share. Silicon Perspective Corp. jumped to a commanding lead in silicon virtual prototyping, displacing Synopsys' Chip Architect. Meanwhile, Mentor came from nowhere in "enterprise" tools to displace Synchronicity in the top spot.

Synopsys still leads the RTL-to-GDSII "IC implementat ion" market, but Magma Design Automation's share grew from 7 to 24 percent. Cadence still holds a slight edge over Avanti in ASIC place and route, and Mentor grew its lead in design-rule checking, mostly at Avanti's expense. But Avanti grabbed the top spot in IC physical analysis, supplanting Synopsys.

Both Mentor and Cadence increased their pcb-layout market shares, with Mentor still holding onto first. Ansoft and Mentor displaced Innoveda as the leaders in pcb analysis and pcb timing, respectively. The only silver lining for Innoveda is an expansion of its lead in signal integrity-that, and the fact that fortunes change rapidly in the volatile EDA industry.