Mixed-signal tools fall short for SoC designs

Mixed-signal tools fall short for SoC designs
By By Henry Chang, Architect, IC Solutions Group, Grant Martin, Fellow of Cadence Labs,Cadence Design Systems Inc., San Jose, Calif.,, EE Times
October 22, 2001 (5:48 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011004S0103

The relentless consumer demand for smaller, cheaper and lower-power products is driving system-on-chip (SoC) designs that combine the fundamental analog, radio frequency (RF), and mixed analog/digital signal components of communications products onto a single integrated circuit (IC), or highly integrated chip set.

These SoC designs generally fall into one of two categories — application-specific integrated circuits (ASIC)-SoC designs, and analog, mixed-signal (AMS)-SoC designs. ASIC-SoC designs emanate from the ASIC design flow, while the roots of AMS-SoC designs lie in the custom IC design flow. Designers of both types strive to integrate as much of the system as possible to reap cost, power and speed benefits.

ASIC-SoC designs are mostly digital and designed as a programmable platform that integrates most of the functions of the end product. They incorporate microprocessors, and possibly digital signal processors, that run the system's e mbedded software. These designs include peripherals (analog and digital) and employ a bus-based architecture. Designers may choose to integrate a limited number of analog and mixed-signal design blocks, but only if it can be done within a reasonable time frame and at a reasonable cost. For example, high-frequency RF is typically handled in a separate chip. New to the traditional ASIC-SoC industry is the growing awareness that most of the development cost of embedded systems comes from designing the embedded software rather than designing the hardware.

AMS-SoC designs began in the realm of custom mixed-signal designs. Typically high-performance designs, these usually include complex signal paths throughout their analog and digital blocks. Examples of such designs include partial-response, maximum likelihood disk-drive controllers, digital subscriber loop front ends, 10/100 Base-T physical layers, and RF front ends. The current era of process technology allows analog and mixed-signal designers to start to integrate significant amounts of the functionality of entire systems into a single chip.

Unlike ASIC-SoC designs, the analog/mixed-signal portion is the critical, differentiating part of the design. In fact,integrating the digital section of the design is optional. With the current generation of process technology, embedded software is not yet a significant issue. The most noteworthy problems stem from the design and integration of digital and analog/mixed-signal blocks. With the increased complexity inherent in AMS-SoC designs, these are thought of as today's "SuperChips."

The design flow for AMS-SoC designs includes many sets of stages. However, not all aspects of design can be neatly separated into discrete stages. There are certain design capabilities and tool requirements that cut across the entire design process. Those requirements may be difficult for EDA tool vendors to address because they do not fall wholly within a specific design stage, and they require interaction between the designers and design tools at each step of the design.

AMS-SoC design incorporates complex feedback loops, with signal paths that cross boundaries between digital and analog blocks multiple times. Designers must account for subtle physical interactions between the analog and digital blocks that cannot be predicted by existing flows. For those reasons, the ad-hoc "patching" of the design process will no longer hold it together. Furthermore, flows consisting of an assortment of point tools will not allow designers to meet their time-to-market objectives for complex AMS-SoC designs.

The challenge of AMS-SoC design requires a holistic approach, where every task in the flow forms part of a comprehensive design solution. The coordination of all design phases results in a new design methodology better suited to the complex design objectives and aggressive time-to-market schedules inherent in AMS-SoC design.

Many EDA ve ndors address one or more stages of AMS-SoC design by offering point tools or mini flows, but do not offer complete integrated flows required for a complex AMS-SoC solution. This correspondingly restricts how much of the problem vendors are able to address. Infrastructure and intertool operation problems cannot be tackled without detailed knowledge of the internal operation of all tools within the flow.

Communication between tools in a complex design flow, along with data integrity, constraint transformations and the simultaneous use of multiple models and levels of abstraction, requires a strong software infrastructure with standards and interfaces to which all applications must adhere.

Many of today's design tools were not developed for the complexity and size of AMS-SoC designs. This is apparent in analog and digital design tools, from front end through physical realization. On the analog side, most tools still target traditional transistor-based, bottom-up design methodologies. These capture-and -analysis tools impose inherent limits on design size. Furthermore, physical realization of analog designs with these tools is largely a manual process.

On the digital side, current generations of tools do not take sufficient account of physical affects during the logical and planning phases. That results in designs that cannot meet their constraints when physically implemented, and so require costly design rework. But while these specific limitations are being addressed at a localized level, the lack of interaction between the digital and analog design processes is far more significant. Digital and analog design tools tend to be targeted only to their specific design methodologies, and they frequently do not take into account the effects of their counterparts. Intertool communication between digital and analog domains frequently uses conflicting standards. This makes it difficult or impossible to create an efficient design flow that maintains data integrity.

EDA vendors must start from scratch if t hey wish to create a truly efficient design environment for AMS-SoC design. The AMS-SoC design methodology must first be defined. A design flow then follows from that resulting methodology. This flow clearly dictates the necessary tools, design representations and data formats required to convey data within each design stage and across various design stages.

A comprehensive "SuperChip" AMS-SoC methodology must be more than just a combination of today's digital and analog design flows. Its scope must expand to embrace system-level design as the starting point for design specification and implementation, and provide cross-domain capabilities such as integration between ICs, chip packages and board design.

The AMS-SoC infrastructure enables the creation of tools that have the necessary functionality and are by definition, plug-and-play components of an efficient overall solution. By restricting the locations to which all tools read and write data, and by defining the allowed formats, it is possible t o insert tools as needed into the flow without having to redesign other components. That approach also makes it possible to create utilities that perform design integrity checks. The infrastructure imposes a restricted set of formats dictated by the required abstraction levels, rather than by the eccentricities of tool designers. The infrastructure greatly reduces the types of checks needed, and confines them to what is required by the design methodology.

Perhaps the most important of these formats will be the mixed-signal hardware description languages (MS-HDLs), such as Verilog-AMS and VHDL-AMS. These give us a common language to represent designs, and most tools — even those from competing vendors — will understand them. Other tools, in addition to simulators, will expand their scope to support one or both of the MS-HDLs. The MS-HDLs are open-standard languages, so the design and EDA communities will be more willing to invest in developing model libraries and support tools for them. MS-HDLs are also likely to develop into a medium of exchange between block authors and block integrators.

Verilog-AMS and VHDL-AMS have been defined, and simulators that support these languages are beginning to appear on the market. The languages will have a significant effect on the design of mixed-signal systems because they provide a single language and simulator that is shared between analog and digital designers. The languages will make it easier to provide a single design flow that naturally supports analog, digital and mixed-signal blocks, and easier for designers to work together. Writing behavioral models for mixed-signal blocks will also become easier. Finally, the AMS languages bring strong, event-driven capabilities to analog simulation and allow designers to write analog event-driven models that inherit the speed and capacity of the digital engines.

As MS-HDLs are being adopted, designers are exploring emerging classes of C/C++-based system design languages, such as SystemC. The extension of th ose to AMS design has been proposed and is under active debate. A more likely scenario for the future is for these C++-based languages to co-exist and interact with the MS-HDLs for both legacy digital designs and the emerging AMS behavioral models. Since the C++-based system design languages will not take designers down into full implementation, defined transition methodologies between high-level specifications and implementations in different language environments will be important.

Over the next few years, the market for large, mixed-signal consumer applications using SoC devices will broaden considerably. Designers must be willing and able to change the way they work. They must broaden their skills to include an understanding of modeling and familiarity with MS-HDLs. Graduate and continuing education must expand to fill this gap.

Some major EDA vendors, including Cadence, are already positioning themselves to provide technology and comprehensive services in the SuperChip design arena. The complex ity of SoC designs for mixed-signal applications requires improvements not just to point tools, but to the entire design methodology. Fundamental to this methodology will be an expansion of scope and an acceptance of new tools and languages for SoC specification and implementation.

The Cadence SuperChip initiative is a multiyear, cooperative effort between Cadence and leading SoC design organizations. The initiative's goal is to provide the most advanced design environment with a scope well beyond traditional analog and digital design flows for complex AMS-SoC designs of 0.13 micron and below.