A look back at the last 10 years of chip design

By Lauro Rizzatti, EVE-USA
EDA DesignLine (06/03/2010 10:18 AM EDT)

The world of integrated circuit (IC) design looks very different than it did 10 years ago, when EVE incorporated and started building its first hardware emulator. In 2000, the semiconductor industry was still reveling in the new millennium and the economy was going strong.

Back then, the process technology node was 180-nanometer (nm) and the average number of transistors in a design was 20 million. The average design size was one-million application specific integrated circuit (ASIC) gates, with large designs coming in at around 10-million ASIC gates and the largest designs at about 100-million ASIC gates. Only a small fraction of the design functionality is derived from the embedded software.

Verification took 70 percent of the project cycle and emulation was used almost exclusively on the large CPU and graphics chip design. EVE’s emulation system in 2000 was able to handle 600,000-ASIC gates and seemed impossibly cutting edge.

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