Embedded test lowers SoC costs

Embedded test lowers SoC costs
By James Fujimoto, Manager, Product Marketing, LogicVision Inc., San Jose, Calif., jfujimoto@logicvision.com , EE Times
August 21, 2001 (1:51 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010816S0079

Advances in very deep-submicron process technology require corresponding investments in design and test. Design infrastructure enabling the achievements of advanced design capability is well understood, yet the investment in test is often overlooked. With increasing device complexity and performance requirements, the "big-iron" test approach requires ever-more-expensive, high-performance testers. These testers, at over $3.5 million apiece for a 512-pin, 400-MHz version, represent a large and significant contribution to the overall cost of a chip. For this capital outlay, integrated-circuit manufacturers can expect a level of capability and functionality that permits higher-frequency application of signals for broad functional test coverage, but in many cases at lower than the needed operating frequency of the device application. Yet, even with these large expenditures in testers the gap between tester frequency and device capability is widening.

With the number of complex, multimillion-gate design starts expected to increase rapidly to greater than 4,000 in the next two to three years, IC design houses and IC manufacturing companies are forced to identify alternative methods to manage the increasingly large costs of test.

Embedded test can help mitigate the need for more complex testers. With embedded test, designers are able to include with their design embedded functions that permit on-chip, at-speed structural test of their silicon devices. These tests-initiated, controlled and evaluated on-chip-provide an internal test mechanism, which reduces the need to scale the big-iron testers to the growth curve of silicon device technology.

Embedded test enables the use of lower-performance testers to provide test coverage at or beyond that expected from the higher-cost testers. In fact, testing a 2 million-plus-gate system-on-chip (SoC) device incorporating a minimum-pin, embedded-test approach at greater than 800 MHz on a $500,000, low-performance tester would yield test coverage comparable to the high-performance tester, but deliver a capital-cost savings advantage of greater than $3 million.

Built-in self-test (BIST)-based products that test memory and logic dominate among embedded-test technologies providing at-speed structural test. Competing approaches to embedded test include scan/automatic test-pattern generation tools that can test at speed.

Embedded test products and ATPG-based products both provide structural test capabilities initiated through an IEEE-1149.1 port. But implementation and usage differences exist with those different approaches. Scan/ATPG products require scan-memory resources resident on the tester to store stimulus and captured data. Their embedded test, BIST-based counterparts have their pattern-generation and comparison functions embedded in the silicon device itself, reducing the feature requirements of the tester.

SoC complicates scan
Memory test capability becomes a s ignificant differentiator as the number of complex, embedded intellectual-property (IP) blocks grows on the silicon devices. Embedded test products, utilizing BIST techniques, can be made to easily scale with hierarchy and complexity with minimal (if any) impact to tester resource requirements. The SCAN/ATPG approach is challenged by increasing complexity and requires significant upgrades to tester resources to accommodate the increase in scan chains and the scan chain depth as the degree of complexity of SoC devices continues to scale.

See related chart

As the use of such third-party IP cores as processors, embedded FPGAs and complex communications cores becomes more prevalent, the self-contained, embedded-test solution for these IP blocks benefits the IC manufacturing companies testing the de vices and the SoC designer integrating the blocks. Dealing with a self-contained, testable block that is usable in a scalable, hierarchical design environment accelerates the test implementation and design closure of these complex pieces of IP in the larger SoC. The design approaches using scan/ATPG products present challenges in implementation and design closure that are separate from the tester resource challenges.

Designers using the scan/ATPG approach need to move off-chip to initiate and compare test data in order to manage a number of variables affecting test time and test quality. For example, the number of scan chains, the depth of the chains and the frequency at which ATPG patterns are applied to the many complex IP blocks are both constraints and variables that the designer must address. The time-consuming manipulation and optimization of these variables during test implementation ultimately result in the trade-offs of test time or test quality for the device.

For the IC manufactur er the benefits of design inclusion of embedded test products or ATPG products is clear: reduced test resource requirements, higher fault coverage over functional fault grading, better yield, better quality. For the designer of the SoC the direct benefit of embedded test is often overlooked.

Embedded test also helps during device validation and debug. Because the embedded test is structural and is implemented based on the connectivity of the design that is implemented on the silicon, the test capability, when applied at speed, can be used to determine if validation failures are due to manufacturing irregularities or timing inaccuracies. This is a benefit in expediting root-cause diagnosis during initial chip validation.