Generating multiple clock frequencies using Specman "real" feature in mixed (Analog/Digital) design environments

Kotasubbarao Sajja, Krishnan Ramakrishnan, Shiju Ullattil
Samsung India Software Operations

Abstract:

Using our “Specman agent approach for the Mixed Verification” along with exploiting “real” feature of Specman version 8.2, we can introduce directed/constrained randomization to the frequencies needed for the analog modules which are interacting with the DUT (Design Under Test). This approach gives complete controllability over the clock frequencies, which can be directly randomized and modified on-the-fly from the testcase, as the scenario may demand. Dependencies across multiple clocks present in the system and their constrained randomizations can also be easily handled with this approach.

Introduction

As the chip industry is churning out SoC’s into the market at a rapid pace, the ever burgeoning time-to-market problem has only worsened further. In order to reach the SoC’s to the customers as early as possible; ways of reducing the entire design and manufacturing cycle of a chip are being constantly evaluated and redefined. As a means of reducing the design cycle time, adding new functionality to previously Silicon-proven designs is being practiced. The key to the success of this incremental design methodology lies on robust and rapid verification of the design. As any design will involve both digital and analog modules, verification of the SoC would involve mimicking the analog operations to reproduce the functionality of the analog blocks present in the system.

Analog blocks rely and operate at precise frequencies and hence the verification tool/language used, must support various floating-point operations. Here two approaches came out to overcome the hurdle and improve the performance. They are

1. Standard Verilog-based approach
2. Specman HVL (High-level Verification Language) based approach.

Traditional Approach

In this Approach, the entire analog block (clock generator) will be coded in verilog. The advantage with verilog is it does support real number definition. But from a verification perspective, verilog is not as powerful as Specman. Verilog also lacks the ability to introduce randomization and reusability when compared to Specman.

Figure 1 Block Diagram for the Traditional Approach

As shown in Figure 1, verilog block is the one which contain the necessary analog logic.

New Approach

For developing the agent in e-language, we have used Specman 8.2 version which supports “real” data type operations. With the help of this feature in ver. 8.2, we were able to generate multiple clocks with precise frequencies (upto 4 decimal points) from Specman, against the usual practice of generating clocks from the Verilog testbench.  

Figure 2 Block Diagram for the New Approach

As per the new approach, the verilog block is replaced by the Specman block as shown in Figure 2. Here, the Specman block will do the necessary analog operation.

Implementation using the New Approach

We have implemented this approach in one of our IP verification activities. The DUT’s functionality is totally based on the frequencies of the input signals. For this verification, we developed a Mixed Analog/Digital agent in e-language which would input multiple signals of varying frequencies to our DUT. Hence, for proper testing of the DUT’s complete functionality, the frequencies of the input signals were extremely critical. Using Specman for the agent, also aided us in easily randomizing the various signals’ frequencies as well as constraining them based on the inter-dependencies of the different signals and their corresponding frequencies. Adding these frequencies into our Specman functional coverage matrix ensured that all the combinations and values of signal frequencies were verified and there were no verification holes.

By exploiting the “real” feature of Specman 8.2, we can model analog modules’ frequencies accurately with higher sophistications such as coverage, randomization etc. when compared to implementing the similar functionality on a Verilog testbench.

In our IP Verification schedule, we were able to finish our activity 7 days ahead of schedule by using this feature in our agent modeling. Also we found couple of critical bugs with this approach.

Generating multiple clock frequencies using Specman

The DUT under consideration is a mixed Digital Analog Block which takes the input clock frequency coming from analog domain and after a series of calculations, uses this input analog clock value to select the particular functionality/feature of the DUT. The clock values have to be precise in order to avoid incorrect/no feature to be selected. Also the DUT clock values needed for selection could be changing from one chip to another as well as the same SoC itself based on added functionality.

Results:

Figure 3 Waveform for the output

Here,

• CLK is the processor clock,
• TD_EN is the enable for the output clcok
• CLK_SEL is the selction for the random clcok
• TD_CLK is output expected.

Here on the fourth clock of the simulation, the clock frequency of the TD_CLK changes to new value based on the random sellection given.

Code Example:

A small code example is given for the usage of the approach.

Here CLK2 is generated based on CLK_FREQ.

Advantages of the New Approach

This approach leads to following advantages.

• The agent approach gives a fully reconfigurable component which can be used from one environment to another with minimal changes in configurability.
• Using the agent, allows the user to use even new values not used in the previous test case.
• Addition of new test cases or changing clock values in existing test cases is far easier and is independent of the language used for developing the verification environment.
• The functional coverage metrics can be identified and collected using this approach which leads to easier tracking and identification of holes in test cases/verification of the DUT.
• Running regression with a wide range of values becomes simple as the sequences are configurable and can be run without any extra manual intervention.
• Scoreboard/reference model implementation becomes ucomplicated with this approach since a series of events as well as flags from the agent can be passed.
• The coverage model and checkers can be turned ON/OFF as well as modified/extended from configuration itself without affecting the base code in case this agent is being reused.

Conclusion

Using our “Specman agent approach for the Mixed Verification” along with exploiting “real” feature of Specman 8.2, we can introduce directed/constrained randomization to the frequencies needed for the analog modules which are interacting with the DUT. This approach gives us complete controllability over the clock frequencies which can be directly randomized and modified on-the-fly from the testcase, as the scenario may demand. Also, it shortens the verification schedule.

Acknowledgement

The authors would to thank Team Media for their assistance in preparing this paper.

References

1. Advanced Verification Techniques: A Systemc Based Approach For Successful Tapeout - Leena Singh, Leonard Drucker, Neyaz Khann
2. IES 8.2 User guide, Cadence.
3. The Functional Verification of Electronic Systems - Brian Bailey
4. eRM Methodology Manual-Cadence
5. Mixed Analog and Digital Verification - Hamilton B. Carter and Shankar Hemmady