More EEs needed to achieve technology gains, exec says

More EEs needed to achieve technology gains, exec says
By Nicolas Mokhoff, EE Times
October 18, 2000 (5:01 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001018S0032

DALLAS — DSPs are the enabling technology that will eventually meld third-generation (3G) phones with the wireless Internet to create a completely wireless world, according to Paul Marino, vice president and director of Motorola Inc.'s DSP Core Technology Center (Austin, Texas), speaking Tuesday (Oct. 17) at the International Conference on Signal Processing Applications and Technology 2000.

Getting there will involve more than overcoming technology barriers, Marino said. It will entail hiring and training more of three different kinds of engineers: IC designers, algorithm developers and software code writers.

Marino claimed that the embedded and computing markets are demanding performance beyond Moore's Law. With 100 million-transistor system-on-chip (SoC) mixed-signal solutions being worked on today, it will take major shifts in various engineering disciplines to produce 10 billion-transistor chips by 2010. He proposed that engineers star t learning the necessary skills for producing 3-D ICs, molecular electronics and CMOS hybrids.

Approaching Amdahl's law of diminishing returns — where a task speedup reaches 80 percent of its maximum, no matter how many simultaneous processors are applied to the task — new techniques and technologies must be applied to hot-button items such as 3G phones, Marino said. There is a gap between the technology that will be needed for 3G phones and what's achievable today, Marino said. Such phones will need to reach the performance level of PCs, which have taken advantage of the increased horsepower of each new processor generation, he said.

Marino called for designers to increasingly focus on design-for-test and validation methodologies, such as the widespread use of built-in self-test and integrated debug logic. "Remember, testing reveals the presence of bugs, not their absence," said Marino. "In the last five years significant recalls of chips were due to the lack of logic verification measures taken early in design."

Marino called, in the short run, for designers to apply virtual emulators on board chips and instruction-set plug-ins as a means for easing SoC design verification. This will be especially important as more embedded memory is included with logic. Predictions state that prime system-on-chip designs will be a 90/10 memory/logic combination. Using embedded memory in volume will close the processor-memory performance gap, which is growing at 44 percent per year, according to a study by the University of California at Berkeley.

Embedding memory successfully requires the systematic use of hardware/software co-simulation tools that allow for the "virtual" integration and debug of software and hardware before hardware prototypes are available. This would also reduce overall development cycle time and help avoid expensive respins of silicon, ASICs and pc-boards. What's more, it would avoid major reworks of software. And with complex DSP applications — one of the most intricate technologies to code properly — growing 10x every ten years in terms of lines of code written, it will be imperative to do system design from the start, Marino said.

DSP applications will be written with some 100,000 lines of code, so getting the job right in the beginning will be paramount, he said.

To generate more interest in DSP applications, Motorola has announced a $100,000 design contest for the best applications described and produced that use the company's 56800 family of DSPs. Fifty application designers will each win $2,000 for presenting new solutions that use DSPs or new ways to perform existing applications. Areas covered by the contest include uninterruptible power controls, adaptive filtering techniques, voice-over-Internet implementation, and digital compression. Details on the contest are available at the Motorola Web site.