Erik Mentze, Sr. Systems Engineer, Cypress Semiconductor Corp.
EETimes (12/23/2010 5:25 PM EST)
Configuring a phase locked loop (PLL) for a given frequency synthesis application can simultaneously be both a quick-and easy-process as well as a time-consuming, tedious, and iterative process. This dual nature in PLL system design arises from the number of loop parameters that need to be appropriately dialed in for a given application. As will be discussed in this article, there are two categories of loop parameters that must be considered: frequency synthesis parameters and performance parameters. The former sets up the loop to generate the correct frequency while the later dictates the quality of output frequency (with “quality” being a term relative to the given application). The interplay between these two categories of parameters is where designers spend the bulk of their time. After determining a set of frequency synthesis parameters that meet the system needs, we then attempt to dial in the performance parameters. However, when we reach the end of optimizing the loop, there is always the doubt: did I choose the best possible frequency synthesis parameters? Perhaps there is a different set that will run cleaner and consume less power or have more margin? It is these design choices upon whicht this paper will attempt to shed some common-sense design principles.
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