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Is there a "one-size fits all" SOC PLL?Jeff Galloway, Randy Caplan A PLL (phase-locked loop) is perhaps the most widely used analog circuit in SOCs (system-on-a-chip). Almost all SOCs with a clock rate over 30MHz use a PLL for frequency synthesis. Most SOCs use more than one PLL, with 3-10 PLLs common. There is a wide range of frequency, power, area, performance, and functionality among PLLs. In advanced SOCs, PLLs range in frequency from 10MHz to 10GHz, a factor of 1000. The power spans sub 1mW to over 100mW, also 100x. The size can vary from 0.04mm2 to 2mm2, a factor of 50. The performance, typically measured as output jitter, ranges from just over 100fs to 10ps or more. Like most types of circuits, there is no such thing as a "one size fits all" PLL. This article will explore the trade-offs in PLL performance and design and look for a solution to most SOC PLL needs. Period and Long Term Jitter There are many reasons for the difference in power and area among PLLs. The most common reason is the jitter performance, although other requirements such as output frequency and loop bandwidth also contribute. The jitter specification is driven by the end use, which could be anything from digital clocking to AFE (analog front end) ADC/DAC clocking to serial link communication to RF synthesis. There are two main types of jitter that system designers should care about, period jitter and long term jitter. Period jitter is the error of a single clock period. More specifically, it is defined as the error seen when the output clock itself is used as the trigger and the jitter is measured at a hold-off time of one output period. Period jitter is usually measured over a large number of samples of the output clock and can be described by a peak-to-peak or root mean square (RMS) number. The period jitter is of concern for static timing analysis in digital circuits. For example, if an engineer needed to clock a circuit at 1GHz, the nominal period would be 1ns. However, no matter how good the PLL is, only the average period will be equal to 1ns. For static timing analysis, the shortest period needs to be known in order to calculate timing margin. Long term jitter, also known as N-cycle jitter or wander, is the measure of how much the PLL output clock edge deviates from the position of an ideal clock over N cycles, where N is typically thousands of cycles. In other words, long term jitter is a measure of the accumulated phase error. Long term jitter is usually measured as an RMS value rather than peak-to-peak. Applications that care about long term jitter include serial link communications with embedded clocks (SONET, XAUI, etc.) and data converter clocking. For serial link communications, the long term jitter is usually specified to be less than 1% RMS of a bit period or unit interval (UI). For example, most 10Gb/s serial interfaces specify an RMS long term jitter of less than 1ps.
 Figure 1. Time Domain Jitter Experiments For data converter clocking, the long term jitter detracts from the signal to noise ratio (SNR) according to SNR = 1/(2*π*f*σ) where f is signal frequency and σ is the RMS long term jitter. Taking as an example a PLL with 5ps of RMS long term jitter, the SNR of an ADC clocked by this PLL is limited to 8b at just over 100MHz and to 14b at just under 2MHz. So, high speed and high resolution ADCs require precise PLLs. Short Term Jitter, Long Term Jitter, and Bandwidth VCO and PLL jitter can be understood by considering the following time domain experiments [2]. These experiments will highlight the differences between long term and short term jitter. They also show the link between VCO phase noise, bandwidth, and jitter. In the first experiment, open loop VCO jitter is measured. In the second experiment, the jitter of a PLL containing the same VCO is measured. In both experiments, the jitter is analyzed by measuring the standard deviation of the zero crossings. The jitter is measured versus time by using N different hold off times from 1*T to N*T, where T is the nominal period. First, the edges of the open loop VCO are measured. The result is shown on the top plot of Figure 1. The standard deviation of the Nth zero crossing is the square root of N times the standard deviation of one cycle (σN=σ1*N1/2). The standard deviation of one cycle, σ1, is the period jitter. The value of σ1 for a VCO is in practice very hard to measure directly due to the jitter of any buffer between the VCO and measurement instrument and the short term jitter of the instrument itself. As N is increased though, the value of σN grows without bound while the RMS jitter of the buffers is bounded. Therefore, the value of σ1 can be extrapolated from a plot of σN versus N. In the second experiment, the edges of a PLL with an ideal reference are measured. For a small number of cycles, the measurements are almost identical to the case of the open loop VCO. After a large number of cycles, the measured standard deviation asymptotically approaches the closed loop standard deviation or long term jitter, σcl. The force that bounds the phase error is the PLL.
There are a few important parameters highlighted on the bottom plot of Figure 1. The closed loop parameter σcl, the long term jitter, is a function of the PLL closed loop bandwidth fL and the period jitter σ1. The closed loop bandwidth is a system design parameter. σL, shown in Figure 1, can be calculated as 1/(2πfL/fvco). The long term jitter is now calculated as σcl=σ1/(4πfL/fvco)1/2 [2]. There are two important results that follow from these experiments. The first result is that short term period jitter depends almost entirely on the VCO (and output buffers) and does not depend on the PLL bandwidth. The second result is that long term jitter depends on both the VCO and the PLL bandwidth, getting better as the VCO improves and bandwidth increases. The above analysis is a simplification in at least two ways. First, the only noise source considered is VCO phase noise. However, most well designed PLLs are VCO noise limited. Note that supply noise or reference noise is not considered here. The second simplification is that the PLL is assumed here to be a first order loop. Most PLLs are at least second order, however many PLLs are over damped and appear almost first order for the sake of this analysis, so the error is not too severe for the sake of first pass hand calculations. VCO Phase Noise and Jitter The previous section shows that long term jitter is influenced by two main factors – PLL bandwidth and VCO jitter (σ1). If low long term jitter is desired, the VCO phase noise should be low and / or the PLL bandwidth high. For many applications, PLL bandwidth is limited (by specification, stability concerns, etc.). In these applications, the PLL jitter is then determined mostly by the VCO performance. Figure 2 shows typical phase noise plots for a pair of equal power 2GHz oscillators consuming several mW. One oscillator is ring based and the other is LC based. There are three distinct regions of operation shown in Figure 2. The most important is the -20dB/decade region. This region typically determines the period jitter of the VCO, σ1. In the simplified analysis for this article, it is assumed that the PLL bandwidth is above the 1/f corner of the VCO, which is not true for all PLLs. The plot also includes a flat region at high frequencies. This is due to VCO output buffers and is important for period jitter but typically not for long term jitter. According to [3], LdB(f)~10*log10[(1/Psig)*( fosc)2/(Q*f) 2]. From this formula the phase noise drops by 3dB for a 2x increase in power. Increasing the power can be an effective way of improving the phase noise performance, but can become expensive. A 10x improvement in phase noise comes at a cost of 100x power increase, with all other things constant. Note also that not all designs of the same power achieve the same phase noise – the design is critically important (topology, biasing, noise isolation, etc.). Another way of improving the phase noise is by choosing a resonant tank. There is roughly 20dB to 30dB difference between the phase noise of a typical ring oscillator and an LC oscillator of the same power in a deep sub micron CMOS processes. This illustrates the phase noise advantage of resonant tank structures for phase noise. As mentioned in the previous section, the value of σ1 can be difficult to measure in the time domain. However, it is relatively straightforward in the frequency domain. The VCO period jitter, σ 1, can be calculated as σ 12=f2*L(f)/fosc3 where f is the offset frequency, L(f) is the phase noise at f, and fosc is the frequency of oscillation [4]. In the example above, the period jitter for the ring VCO with -100dBc/Hz at 1MHz offset and 2GHz oscillation frequency is 112fs RMS. The LC oscillator with -125dBc/Hz at 1MHz offset and 2GHz oscillation frequency results in σ 1 of 6.3fs RMS. These values are typically too small to measure directly in the time domain and obscured by buffer and scope noise. Long Term Jitter and Bandwidth Examples Using the relationship between period jitter, bandwidth, and long term jitter above, the ring VCO example with σ 1=112fs and 100kHz PLL bandwidth would have approximately 4.5ps RMS long term jitter while the LC VCO example with σ 1=6.3fs would have a long term jitter of 270fs RMS. If the bandwidth were increased to 1MHz, then both long term jitter values would decrease by sqrt(10) to 1.4ps and 85fs respectively. These calculations could be continued for higher and higher bandwidths, but there are many reasons why the bandwidth must be limited and the jitter would not continue to decrease. Figure 3 shows a Silicon Creations Fractional-N S-Band frequency synthesizer in 90nm CMOS and the associated phase noise / jitter measurement. This PLL achieves some of the best phase noise and jitter performance reported for a monolithic PLL. The measurement shows 252fs RMS long term jitter with a 30kHz bandwidth. The PLL is measured in fractional-N mode (multiply by 55.375). Note that the above simplified long term jitter calculations for this synthesizer with phase noise of -130.7dBc/Hz at 1MHz offset, 2215MHz carrier, and 30kHz bandwidth would yield 215fs, close to the 252fs measured. Figure 3. LCPLL phase noise Although the S-Band synthesizer described meets the jitter required by even the most stringent specifications, the power and area are undesirable for many SOC applications. Figure 4 shows a schematic of Silicon Creations ring-based Fractional-N PLL standard product. This product is designed for a majority of the standard SOC applications that require good long term jitter. The PLL is designed with a built in ΔΣ modulator and noise canceling DAC for demanding applications. It is designed to be widely programmable, either as an integer-N or fractional-N PLL. The VCO phase noise is -102dBc/Hz at 1MHz offset while the bandwidth varies from around 100kHz (fractional-N mode) to 1MHz (integer-N mode), and scales with the reference clock. The long term jitter depends on the programming, but is typically 3-10ps RMS while consuming 5mW typical and 0.07mm2. The ΔΣ modulator allows for additional flexibility. Spread spectrum or FM/PM modulation can be achieved with an external, all digital modulator that runs at the reference clock rate (e.g. 20MHz). Due to it's low power and area plus wide programming range, the Silicon Creations Fractional-N PLL standard product can be a single PLL solution for most SOCs. Typical Silicon Creations customers use multiple instances of the PLL standard product on the same SOC to clock ADCs, DACs, DDR PHYs, Ethernet PHYs, ARM® cores, custom logic, etc. It is available in most 40nm to 180nm processes. Summary This article has explored some of the trade-offs associated with SOC PLLs. The driving factor for many of the trade-offs is the long term jitter. For most SOCs, a power and jitter optimized ring-based PLL can be a solution for all PLL needs. Silicon Creations offers PLLs ranging from PLLs with the most stringent jitter performance to power and jitter optimized multi-purpose PLLs. Figure 4. Multi-Function ΔΣbased PLL Information about ring-based PLLs: References [1] Phaselock Techniques, Floyd M. Gardner, 3rd edition, 2005, John Wiley & Sons Author Information Jeff Galloway is a co-founder of Silicon Creations and is responsible for analog IP design and development. Prior to founding Silicon Creations, he held various positions at Hewlett-Packard, Agilent Laboratories, and MOSAID. He holds a BS in Electrical Engineering from Georgia Tech with Highest Honors and a MS in Electrical Engineering from Stanford University. He has 11 issued U.S. Patents with others pending. Randy Caplan is President and Co-Founder of Silicon Creations. He has led the development of Silicon Creatons' high performance clocking IP product line which includes over 40 unique timing solutions for applications such as SONET, PCIe, Infiniband, SATA and IEEE 802.11b/g/n. Prior to founding Silicon Creations, he was the senior PLL architect at Mosaid and Virtual Silicon, and lead SerDes designer in the High Speed Networking group at HP/Agilent. Randy has three patents in the areas of PLL design and analog circuit design.
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