How to instrument your design with simple SystemVerilog assertions

Ping Yeung, Ph.D., Mentor Graphics Corp.
1/26/2011 10:19 AM EST

Introduction

Functional coverage, stimulus generation, and run management are the three major interrelated tasks of functional verification today. Among these, functional coverage arguably looms as the most important, largely because coverage closure is the main criteria for tapeout. Measures of coverage provide critical feedback, such as the existence of gaps. As shown in figure 1, a comprehensive coverage model should consist of end-to-end functional coverage, transaction coverage on major interfaces, structural coverage of critical RTL structures and basic code coverage.

Figure 1: A comprehensive coverage model

An assertion-based methodology helps catch bugs, audit the quality of the regression environment and guard against illegal module use. Such a methodology need not be developed by the verification team alone. Designers can provide significant value by capturing their intimate knowledge about the internal operations of the design in the form of assertions.

Assertions and functional coverage are really two sides of the same coin [1]. Both provide detailed observation points within a register transfer level (RTL) design. And while assertions’ design checking attributes are well known, the additional benefit -- supplementing functional coverage measurement -- is frequently overlooked by design teams. It turns out that the task of placing assertions in a design is similar to the task of finding interesting and relevant functional coverage points. Accordingly, it often makes sense to add assertions and coverage points concurrently.

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