Ease production at 65nm with DFM

Jean-Marie Brunet, Mentor Graphics Corp., Mark Redford, Colin Thomas and Mark Scoones, Cambridge Silicon Radio
EETimes (2/15/2011 11:23 PM EST)

The challenges of production at advanced process geometries are well-known. In anticipation of reaching today's leading-edge process nodes, electronic design automation (EDA) companies and chip foundries have been developing and perfecting design-for-manufacturing (DFM) technology to address users' critical needs. However, many designers viewed these DFM tools with skepticism as they continued to get products to market without them.

Two new factors now influence the use of DFM for integrated circuit (IC) development at 65nm and below. First, foundries now require or strongly recommend DFM checks, essentially equating them to traditional design rule checks. This requirement implies a shift in responsibility—customers not employing DFM checks during design verification may find the foundry less willing to address yield issues when the product goes into volume manufacturing. Second, some companies have discovered that DFM can be a source of competitive advantage, and are aggressively deploying it to wring more performance out of and/or increase reliability of their designs at leading-edge process nodes.

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