SoCs: Supporting Socketization -> Reuse goal : fast tapeouts

Reuse goal: fast tapeouts
By Jeff Jussel, Director, Mentor Graphics', Consulting Division, San Jose, Calif., EE Times
January 3, 2000 (3:13 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000103S0045

Reuse environments typically include a Web-based system that allows system-on-chip (SoC) designers to search and select intellectual property (IP) from a list of available components. This should be more than a catalog, however. The environment needs an intelligent database that supports managing and protecting the design data. It should also enforce a certification procedure. Although automation of the certification is a plus, a clearly defined process that communicates the IP status to the designer is even more essential.

Going a step beyond the IP database, solutions such as Mentor Graphics' QuickUse Development System actually encapsulate the SoC design flow to provide the necessary link between design standards and tool flows. The QuickUse design-process control system manages the flow of data, and provides the designer with the appropriate IP deliverables for each design stage. By injecting knowledge of the system-design requirements, the QuickUse environment can also automate many of the SoC integration tasks, including top-level netlist generation and functional verification.

Toshiba (Irvine, Calif.) uses an environment based on QuickUse to build SoC designs from existing IP. "We succeeded in reducing our SoC design cycles for 16- and 32-bit microcomputers to as little as five days," said EDA manager Tamotsu Hiwatashi. "The main point to emphasize is the accelerated time-to-market."

The system assembles the chip automatically-connecting IP, generating address decode logic and adding I/O ports. Tool scripts are also generated automatically using easily replaceable software plug-ins. Thus, Toshiba engineers can use their existing tool flow, while maintaining design tool independence.

Hiwatashi said the system is easy for all the engineers to use. "Even those with little experience can understand the flow and create high-quality systems," he said.

The Mentor QuickUse environment generates parameterized v ectors to automatically perform chip-level interconnect verification. As each block is added to the system, the design flow is modified to include the interconnect test for that block. The system then runs the verification suite automatically. This avoids forcing designers to re-create test suites for unfamiliar designs in order to test them in the chip.

Thanks to solutions like QuickUse, the long-promised gains of design reuse are becoming a reality.