Major changes expected for physical verification tools as designs move into 28nm and below

Vlad Marchuk, CTO and founder, PolytEDA Software Corp.
EETimes (3/8/2011 6:05 AM EST)

The semiconductor industry continues to shrink process technologies to geometries way below the wavelength of the light source used to create the patterns on a wafer. Starting at geometries such as 40nm, designers who never had to think about semiconductor manufacturing process-related issues were forced to consider complex physics, in addition to the geometric growth in data size during design implementation. That is a lot of learning to do in a short time for designers, and the pressure will continue. 28nm technology is around the corner and 20nm process will soon follow.

As the semiconductor industry is charging forward with its process technologies, the electronic design automation (EDA) industry is trying to keep in step with the process advances. While EDA tools have done a reasonably good job of keeping up, the recent trends in process technologies have created new needs, for instance, the need to move from a compute farm to a compute “ranch” for physical verification. And still runtimes take several hours, or even days. Most of these tools were architected using algorithms and concepts that were developed in the 1990s (some even in the 1980s) and are unable to meet the runtime and scalability needs for the advanced process technologies, today and tomorrow.

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