Minimize leakage power in embedded SoC designs with Multi-Vt cells

Abhishek Mahajan and Sorabh Sachdeva, Freescale Semiconductor
EETimes (8/6/2011 5:03 PM EDT)

The authors describe the use of a multithreshold voltage (Multi-Vt) flow technique that does not require embedded SoC architecture changes and allows a designer to decide when to use Low-Vt cells, which have better timing but higher leakage power, and when to use High-Vt cells which have lower leakage but worse timing.

Minimizing leakage power in systems-on-chip (SoCs) has become a major priority for designers because it increases drastically in submicron process technologies, becoming a major proportion of power usage. There are various design techniques to optimize dynamic power, such as power gating and dynamic voltage and frequency scaling (DVFS), but these require architectural changes that add to chip complexity, which you want to avoid in SoCs. Multiple voltage threshold (Multi-Vt) flow is the only technique that doesn’t require changes to the SoC architecture; it depends instead on how judiciously the designer uses Low-Vt cells. Low-Vt cells have better timing but higher leakage power; High-Vt cells have lower leakage but worse timing.

To minimize leakage power, Multi-Vt cells are used during the logical synthesis stage of the design (Figure 1 below). Since High-Vt cells have more delays, these cells are used where timing is relaxed, whereas Std-Vt and Low-Vt cells are used at timing-critical places. The expectation is always to meet timing with optimal area and power. The important point here is that priority is still given to timing as logic synthesis is done at the worst process voltage temperature (PVT), i.e. WCS-HOT (worst case timing at maximum temperature), where delay of the cells is maximum.  (In Figure 1 RTL refers to register transfer level). 

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