Reducing Turnaround Time with Hierarchical Timing Analysis

Sunil Walia, Synopsys
EETimes (10/3/2011 10:32 AM EDT)

The semiconductor industry accepts two facts: designs continue to grow in size and complexity, and time-to-market pressure is higher than ever. I’ll use the ‘smart phone’ as an example to make my point. On a smart phone you can now talk, text, IM, take pictures and videos, play games and perform a host of other tasks. Question: How is this possible? Answer: By integrating multiple functionalities capable of simultaneous interaction onto a single chip. Question: How do you make this happen within the same amount of time you are given as the last chip? Answer: Design reuse.

As design evolution continues, packing lots more on a single die, ‘design reuse’ has become a common technique. There is reuse of IPs, flows, and methodologies – all causing the design size growth to sometimes surpass Moore’s Law. However, designers are feeling the squeeze between packing tons of functionality on one end and experiencing no relaxation in time-to-market requirements at the other. Market dynamics dictate that if you snooze, you lose.

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