Dream of interoperable IP butts up against reality

Dream of interoperable IP butts up against reality
By Michael Santarini, EE Times
March 18, 2002 (10:51 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020318S0015

SANTARINI_MIKE Although the worldwide market for semiconductor intellectual property (IP) is growing 20 percent a year, efforts to establish open IP trading have been hindered by instability and self-recrimination, according to participants in a recent panel at the Design Automation and Test in Europe conference in Paris. The lack of "verifiable" standards, poorly made IP that doesn't map well into silicon and IP vendors that are perceived as unstable are among the issues holding back the industry's vision of openly available, interoperable, plug-and-play IP cores, the panelists said.

Further, the industry may have vastly underestimated what's needed to implement a system of reusable virtual components, some panel members suggested.

"The idea of virtual components that are reusable in any environment without redesign was naive," Larry Rosenberg, technical chairman of the Virtual Socket Interface Alliance (VSIA), said, speaking from the audience. Individual IP cores have too many unpredictable elements that are hard to change or fix when dropped into a system-level design, he said. Dealing with IP blocks is "a little bit too low-level," Rosenberg said. "We have to move up a level to a platform design." The VSIA has just launched a study group on platform design to explore how it may help the reusability of virtual components, he said.

Panelist Andy Travers, chief executive officer at the Virtual Component Exchange (VCX), called the idea of easy interoperable-system design by means of plug-in IP blocks "a self-fulfilling fantasy created by the demand side." Some of the standardization work carried out within the VSIA has exposed complex underlying technology issues, Travers said. He too called for "some kind of platform approach."

Asked which standards must be further specified to set IP trading in motion, Tim Daniel s, ASIC product-marketing manager at LSI Logic Europe (Berkshire, U.K.), said that testbenches are "still a big issue" and lack sufficient external standards. "IP is not a dog food sold in a supermarket," Daniels said. "IP has to come with a rigorous methodology and testbench so that we can make sure the IP works in an FPGA, and eventually in an ASIC." Pierre Bricaud, responsible for SoC strategic relationships at Mentor Graphics Europe (Sophia-Antipolis, France), concurred that "Standards must be verifiable and checkable."

The matter is complicated further, VCX's Travers said, because "there is a vast range of interpretation of standards."

Jim Tully, chief semiconductor analyst at Gartner Dataquest (Surrey, England), asked the panel why there are no takers so far for IP-evaluation services. The answer: IP buyers demand proof. "We've heard it loud and clear from many IP buyers, especially from Japan, that they won't talk to IP providers unless they've seen it in hardware," Travers said.

Pat Mead, technical-marketing manager at Altera Europe (Buckinghamshire, U.K.), advised the IP vendors to "get yourself a programmable platform. Building [your IP] on an FPGA will serve as a huge confidence builder and raise the visibility of your IP." Mentor's Bricaud bluntly noted, "If it hasn't seen hardware, your IP won't be worth much." John Heighton, with IP and services marketing at Xilinx Europe (Surrey), noted that poorly made IP in particular requires a strong support team to sort out integration issues.

-Contributed by Junko Yoshida, edited by Michael Santarini.