Signal Integrity --> Signal models fine-tune designs

Signal models fine-tune designs
By Rajit Chandra, Director of Technology, Magma Design Automation Inc., Cupertino, Calif., EE Times
March 25, 2002 (10:31 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020322S0063

Signal integrity effects are becoming increasingly significant as deep-submicron geometries continue to shrink. But to eliminate signal integrity (SI) violations with conventional point-tool solutions, overly conservative implementation practices are used-sometimes with inaccurate verification techniques-resulting in device performance that is well below the silicon's full potential. This is not an option in today's highly competitive marketplace.

Timing closure and functional verification cannot be considered complete until postlayout SI effects have been fully accounted for. Effects like crosstalk (noise and timing) and voltage drop have complex interdependencies, and conventional tools often cannot consider all of them, and their interrelationships, at the same time. However, with accurate modeling techniques and an integrated approach, sign-off-quality SI verification is possible.

Today's deep-submicron implementation technologies a re dominated by interconnect delays. This means any changes in signal behavior can have a major effect on the quality of the design. In deep-submicron design, increased sidewall capacitive coupling emerges as the interconnect aspect ratio (width to height) changes. Previously, track width was greater than the height, but as feature sizes continue to shrink track height predominates over width.

As a result, coupling capacitance, or CXCOUP, increases between the sidewalls of adjacent tracks relative to the substrate capacitances CAREA (track base to substrate) and CFRINGE (sidewall to substrate).

The combination of these factors results in more crosstalk noise and complex timing effects. First, there are crosstalk-induced glitches. When signals in neighboring wires make a transition between logic values, the coupling capacitance between the wires causes a transfer of charge. Depending on the slew and CXTALK there can be significant cross-talk-induced glitches.

If the ensuing noise gli tches on the victim net cross the input-switching threshold of its receiver, a functional error may occur and may manifest itself as an incorrect data value that is subsequently loaded into a register or latch. There are several types of crosstalk-induced timing errors. When simultaneous switching occurs on both the aggressor and victim nets the signal on the victim net may be slowed or sped. This can result in a downstream setup-or-hold violation on the affected logic.

The flow of current through the resistive power rails causes significant IR drop in today's designs. Voltage drops can produce their own timing anomalies and glitches.

Implementation-level SI analytical models are based on macro models containing abstracted transistor-level behavior; such models allow for fast but conservative computation of SI effects. However, this may not be suitable for sign-off verification, which requires an analysis of SI concerns based on highly detailed information. Although SI analysis appears in bo th the implementation and sign-off verification phases, the requirements for each phase are significantly different.

Key design flow requirements for sign-off verification include the following:

Work with standard formats and interfaces so as to fit into existing implementation flows.
Be able to handle today's multimillion-gate designs in a timely manner.
Efficiently filter out nonproblem areas without missing any violations.
Fully support hierarchical design flows.
Provide the modeling capability necessary to support the integration of third-party intellectual property (memory blocks, hard macros, cores).

If the sign-off verification solution is appropriately detailed, accurate and comprehensive, slower run-times will be tolerated. Such accuracy may make it possible to detect new violations caused by the interdependent effects of SI-and the confidence would eliminate unnecessary design changes.

The sign-off verification tools must use highly accu rate models and must integrate advanced analysis tools, such as:

A distributed parasitic model that takes account of edge-rate degradation.
A sophisticated multi-aggressor model that takes account of overlapping timing windows to filter nonproblems and identify worst-case problems.
Less pessimistic glitch analysis that takes account of noise pulses' width and height.
The ability to concurrently consider crosstalk (both noise and timing), voltage drop (IR drop) and their interrelationships.
Provide Spice-level accuracy of crosstalk effects where necessary while maintaining efficiency by automatically using reduced-order modeling of nondominant aggressors.

A distributed parasitic model provides higher accuracy than a lumped parasitic model. Accurate accounting for edge-rate degradation and holding-resistance variation ensures that no noise violation is missed and false errors are kept to a minimum.

Conventional noise-analysis tools usually interface with ex ternal timing-analysis capabilities in order to determine the set of aggressor nets to be considered. They do not consider the victim net's timing requirements and can therefore yield false errors through overly pessimistic analysis. For sign-off analysis, a more sophisticated multi-aggressor model is required. An SI verification solution with an integrated timer will provide improved accuracy to adjust for the circular dependency between signal arrival times and the effective capacitance values between victim and aggressor nets and flow efficiency.

See related chart