FPGA testing for DO-254 compliance

Louie De Luna, Aldec DO-254 program manager
EETimes (5/22/2012 4:10 AM EDT)

The stringent design assurance guideline imposed by DO-254 for custom micro-coded devices like FPGAs present significant verification challenges within the avionics community. As the complexity of the FPGA design increases, so does the verification activities needed to satisfy the verification objectives of DO-254. As defined in the guidance, verification process activities may be satisfied through a combination of methods such as peer reviews, simulation analyses and tests. For design assurance level (DAL) A and B, it is critical that all FPGA pin-level requirements are verified through simulation and hardware tests and evidence of results documented and provided.

This article describes several significant challenges that can be encountered when verifying FPGA pin-level requirements during board level testing under DO-254 guidelines. More importantly, this article proposes a methodology that augments board level testing to overcome these challenges.

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