Control dominated design

Mike Meredith, Forte Design Systems
EETimes (7/14/2012 11:16 AM EDT)

One of the things that jumped out at me on the floor and in the suites at DAC this year was how many people asked something like "I've heard that HLS can be used for control-dominated stuff now. Explain to me how that's possible."

In this article, I'll try to do that.

What is a control-dominated design?

So, what exactly is a control-dominated design? Unfortunately I'm not able to give as precise a definition as I'd like.

One definition that makes sense to me is "A control-dominated design is one in which the complexity of the resulting hardware is more related to I/O and memory accesses than to computation."

Another, more prosaic, definition I like is "A datapath-dominated design is about deriving new data values from previous data values. A control-dominated design is about moving data values around."

Is control-dominated SystemC code really at a higher level of abstraction than RTL?

It certainly is. The key improvements in the abstraction level come from the ability to use an implicit state machine representation and the encapsulation and scheduling of I/O and memory access protocols.

As an example, here's an excerpt from the instruction fetch and decode logic of an 8051 processor. Note that the state machine is explicit. Also note that the memory access protocols have been broken into phases that are manually scheduled. The RAM has a 1 cycle read latency, while the ROM has a 2 cycle read latency.

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