Configurable dividers for SOC / block-level clocking

Prateek Gupta, Priyanka Garg - Freescale
EETimes (9/4/2012 9:08 AM EDT)

Clocking constitutes one of the most important aspect of block or SOC-level design and its architecture needs to well defined and understood during the conceptualizing/planning phase of the design. In a single SOC there are various blocks such as core, flash, memories and peripherals which need to be run at a different frequency. The maximum operational rates may be limited by the implementation technology used, the implementation architecture, power targets and access time of the IPs. Clock divider circuitry is necessary that can generate divided clocks from the master PLL /oscillator clock, or any system clock, and feed different divided clocks to different device modules. As clocking can also be application driven, the clock dividers must be configurable. The need for configurability might arise for a number of reasons including:

• Running the system clock at a lower frequency to save on dynamic power dissipation
• Running state machine of peripherals at a higher/lower frequency than that of the processor
• Setting the baud rate for peripheral frame transmission/reception.

This article illustrates various implementations of configurable clock divider logic used in SOCs today and highlights their challenges, advantages or limitations over the others. There are various implementations of configurable division; however the simplest and the most frequently used in the digital design industry are:

• Ripple Dividers
• Div decode based 2N dividers with 50% duty cycle
• Clock gating enable-based integer dividers which do not have 50% duty cycle
• Mux based dividers with integer division and 50% duty cycle.

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