Designing a reset-aware OVM testbench

Bahaa Osman - Intel
9/24/2012 9:42 AM EDT

Introduction

Reset is a state that exists for almost every single IP, and is usually controlled by at least one, in some cases more, input signal. Typically, a design starts in the reset state and when the reset signal is deasserted; the IP comes out of the reset state and walks through into its functional states. The reset state may be also the state which the IP starts in when powered up after being power gated. In addition, the IP might need to be reset during run-time for various reasons, either functional reasons such as power gating/power up or recovering from incorrect behavior. An IP can be reset during operation for verification purposes as well, to check that the IP will behave gracefully if reset is asserted at any time while the IP is running. All the above makes the reset state and the signals affecting it of great concern to the verification of the IP. The verification environment designed to verify the IP is required not only to be aware of the reset state and signals causing any state transition to and out of this state, but also be able to verify the IP behaved as expected when going into and coming out of the reset state. This paper describes how to design your testbench to make it reset-aware, starting by discussing how this affects the testbench architecture, and then going into more details about each verification component and what changes are required for it to take into consideration the reset conditions.

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