Gurinder Singh Baghria, Kushagra Khorwal, Naveen Kumar - Freescale
EETimes (12/27/2012 11:10 AM EST)
In the competitive semiconductor world, most of the organization tries to put many applications and features into a single design. To come up with the demanding multi-featured design, SoCs are getting complex and a need to perform the design hierarchically arises. In deep sub-micron technology nodes, the biggest challenge in hierarchical design is signal routing closure for the top level which have huge number of partitions, and to decide the target standard cell utilization for partitions. During the initial phase of the design cycle it is very difficult to predict the standard cell utilization for the hierarchical sub-blocks/partitions. Over or under estimation/planning in allotting area between sub-partitions will lead to die area wastage or a cycle time hit respectively. Efficient planning for complex designs is necessary for on time design closure and deployment of a flexible and novel partitioning strategy which is described in this paper. It helps to reduce late stage surprises such as routing congestion at the top level without entering into an iterative process by using virtual area reduction for sub partitions.
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