Debugging FPGA-based video systems: Part 2

Andrew Draper, Altera Corp.
Embedded.com (June 2, 2013)

Most digital video protocols send video frames between boards using a clock and a series of synchronization signals. This is simple to explain but it is an inefficient way to communicate within a device, as all processing modules need to be ready to process data on every clock within the frame, but will be idle during the synchronization intervals.

Using a flow-controlled interface is more flexible because it simplifies processing blocks and allows them to spread the data processing over the whole frame time. Flow-controlled interfaces provide a way to control the flow of data in both directions e the source can indicate on which cycles there is data present and can backpressure when it is not ready to accept data.

In the Avalon ST flow-controlled interface the valid signal indicates that the source has data and the ready signal indicates that the sink is able to accept it (i.e. is not backpressuring the source).

If you are building a system from library components, most problems will occur when converting from clocked-video streams to flow-controlled video streams, and vice versa.

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