Scaling NAND flash to 20-nm node and beyond

Nirmal Ramaswamy, Thomas Graettinger, et al., Micron Technology Inc.
EETimes (6/10/2013 2:22 PM EDT)

Abstract

Intel-Micron have recently introduced a scalable planar NAND cell for the 20nm technology [1]. Replacement of conventional wrap floating gate (FG) NAND memory cell with a High-K/Metal gate planar cell that can scale to the 20nm node and beyond was a significant challenge and required comprehensive material and cell exploration and optimization. This paper discusses some of the fundamental cell design issues considered and addressed to arrive at this planar cell technology including the reasoning behind choosing the planar floating gate cell over the nano-crystal cell, and the nitride cell.

Introduction

Symmetric scaling of the conventional floating gate (FG) NAND cell below the 25 nm node poses significant challenges [2]. The most fundamental of these challenges is in scaling the cell width due to the requirement of being able to fit the control gate between two cells. Shaping the floating gate and control gate has been proposed as solution for this problem [3]. However, even if such floating gate and control gate shaping can be physically produced, the NAND cell could still suffer from very high electric fields at the narrow tips of the gates resulting in poor cell reliability. Additionally structural stabilities due to the high aspect ratio can be an issue at such small geometries [4]. Another key challenge faced with scaling is the increased cell to cell interference due to shrinking dimensions [5].

This had already become a problem at the 25nm node requiring the deployment of airgap between the cells to reduce interference [6], leaving only incremental opportunities for interference reduction as the cell pitch is further scaled. Because of these issues, a planar NAND cell has been considered as the solution for continued scaling [7, 8]. A planar cell, by definition, does not require the control gate to wrap around the floating gate and as a result removes this very fundamental and physical cell width scaling limitation. Additionally, planar cell allows scaling of the charge storage node thickness which can be very helpful in reducing the cell to cell interference.

Many planar NAND cell options have been discussed in the literature [7-11]. These have predominantly been of the nature of nitride or nano-crystal charge trap cell, though some work has been reported on thin conductive floating gate cells as well. The perceived advantage of nitride or nano-crystal charge storage was that the discrete nature of the charge storage could help make the cell more immune to localized charge loss issues such as those stemming from oxide defects including Stress Induced Leakage Current (SILC). Common requirement of all these planar cells, whether they use nitride, nano-crystal, or thin conductive floating gate for charge storage has been a high-K blocking dielectric. Planar cells do not have the intrinsic advantage of a “wrap” that enables an ONO dielectric in a conventional floating gate cell. Hence, the blocking dielectric has to be composed of high-k material to compensate for the lack of “wrap”. NAND cell operation requires deeply negative erase threshold voltage. Even with the use of high-K dielectric for the blocking dielectric, back injection from the control gate during erase can limit the erase threshold voltage unless a high work function material (that can withstand high back end thermal budget) is used for the control gate.

Despite all the work on realizing a planar NAND cell technology, the only planar MLC NAND technology currently in production is the Intel-Micron 20nm technology [1]. This paper will describe the fundamental issues with the various alternative approaches and discuss the planar cell technology that successfully overcame these issues to enable mass production of a symmetrically scaled 20nm cell.

Click here to read more ...

E-mail This Article

Printer-Friendly Page