An Oversampling Technique for Serial Protocols

Chowdhary Musunuri, Director, Engineering Solutions, SoC Product Group, Microsemi
10/7/2013 04:15 PM EDT

Serial communication has long been an effective way of transmitting data with a minimum set of wires across long cables and different media. The serial data links that are in use vary in both transmission speeds and protocols. New serial protocols are constantly being brought to market. FPGAs with embedded SERDES blocks coupled with reconfigurable logic are effective in handling a wide range of serial communication protocols.

FPGA blocks typically embed high-speed analog SERDES blocks that work within a fixed range of data rates. Because of internal PLL operating range limitations, the lower cutoff data rate with these high-speed SERDES blocks is typically around 1,000 Mbit/s. However, there are several serial protocols that operate below that. Take the commonly used IEEE1394 protocol that extends its operating data rate from 400 Mbit/s to 3.2 Gbit/s. To support the lower data rates of such protocols, an oversampling technique can be used. In this technique, each data bit is sampled in multiple clock cycles before being transmitted. For instance, to transmit a 400 Mbit/s data rate over a serial link that supports 1 Gbit/s or above, each bit can be sampled three times and spread over three clock cycles. This is called 3x oversampling. Using this technique, lower data rates can be transmitted while the SERDES PLL continues to run within its valid operating range.

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