Naman Gupta and Rohit Goyal, Freescale Semiconductor, Noida, India
embedded.com (December 4, 2013)
Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is often misconstrued to be a magical solution to the meet timing requirements. While it is undoubtedly the responsibility of STA engineers to close the timing, it is equally important for the register transfer level (RTL) designers to avoid some conspicuous errors, which we refer to as architectural pitfalls for timing.
In this article we discuss AND-gate clock gating and OR-gate clock gating use cases, some obvious and some not-so-obvious, which can serve as a guide to designers to ensure that such situations are avoided upfront in the RTL stage and thus preclude the reiteration of timing closure activities from, let’s say, clock tree synthesis (CTS) and back to logical synthesis.
We conclude the paper with a case study of an odd-frequency divider circuit that has one implementation that yields correct results in RTL simulation and the necessary changes in the algorithm to ensure that it works well on silicon.
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