Shaving power/area with merged logic in SoC designs

Shilpa Gupta and Gaurav Goyal, Freescale Semiconductor
EDN (December 31, 2013)

In the modern era, there is always a requirement to achieve high frequency with lower power consumption. Achieving both targets simultaneously is very difficult and the situation becomes even more complex while moving down the technology nodes due to various sub-micron effects. A low power solution becomes more urgent as more and more complex features are integrated into any SoC. More features dictate the need for more logic and hence more die size, which eventually affects chip cost. Consequently, it is extremely necessary to have a technique that would be able to reduce the logic without affecting any performance parameter while keeping power in check.

Designers often find the need to include many instances of the same IP in designs. When the identical modules are instantiated twice, the same combinational (combo) logic and flip-flops are of course instantiated twice. So, instead of replicating the whole module, designers can save silicon area/gate count if they have a way to share the combo logic between two IPs. The proposed architecture is a flip-flop design that can reduce the replicated logic in any SoC -- resulting in lower area and power and, accordingly, further reducing the chip cost. Figure 1 depicts the prior and proposed approach of integrating two duplicated IPs in any SoC.

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