David Stratman, Sanjiv Taneja (Cadence)
EDN (December 16, 2013)
The small world of sub-20nm design is already upon us and has brought a new set of challenges for register-transfer level (RTL) designers as the race for best performance, power, and area (PPA) continues unabated. Challenges include giga-scale integration of new functionality; new physics effects; new device structures such as FinFETs, multi-Vt and multi-channel devices; interconnect stacks with vastly varying resistance characteristics between the top and bottom layers; and process variation.
These challenges are raising several questions. For example, can RTL synthesis handle giga-scale, giga-hertz designs in a timeframe of market relevance? Can logic synthesis perform accurate and predictive modeling of the interconnect stack and the physical effects in RTL? How do new device structures affect dynamic and leakage power tradeoff and library choices? This paper will explore these challenges and provide an overview of state-of-the-art technology to address them in a predictable and convergent design flow.
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