Overcome memory-imposed access rate and bandwidth constraints

Michael S., Mosys
EDN (January 13, 2014)

Design teams building high-speed, next-generation network communications equipment suffer under the constraints imposed by memory. Some design solutions use only on-chip memory which is inherently limited in capacity and competes with silicon area that could be otherwise used for computation or other functionality. More complex applications require external memory and at the processing rates available today need the highest possible random access rate to that memory. Traditional memory interfaces are a burden to performance because they are plagued by slow speeds, lengthy latency, and high pin counts. As a result, conventional design approaches to implementing external memory have already reached the point of diminishing returns.

Serial Protocols and Standards Break the I/O Bottleneck

Consider any modern System-on-Chip (SoC) available today and you will see nearly all the interfaces are serial, except for that to traditional memory ICs. Going forward, the transition to serial memory has already begun and decisions need to be made regarding which serial interface protocols to support. Any interface can be delineated into its physical layer or PHY, transport protocol or PCS, and transaction layer or the command set. Standardization can take place on each level independently.

Regarding the serial PHY; the industry standards group, the Optical Internetworking Forum (OIF), published the Common Electrical Interface I/O (CEI) standards including CEI-11 in September 2011.¹ Standards development groups such as OIF require three to five years to develop channel models, set clocking and jitter budgets, determine electrical signal coding, and encourage the development of the ecosystem. As a result, these standards are being adopted for a broad range of applications

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