Design Tip: Implementing an SoC with dependable 50% duty cycles

Rohit Goyal & Ambuj Goyal (Freescale)
Embedded.com (January 26, 2014)

With the increased integration and movement towards system-on-chip (SoC) designs, it is becoming increasingly challenging to satisfy the diverse clocking requirements of the ever increasing functions and Intellectual Property (IP) circuit blocks. Along with this come diverse clocking needs, ranging from frequency and phase relationships to fulfill jitter specs, sequencing of clock enables, and the lie (layout of the circuit). A multitude of clock frequencies are needed to satisfy the needs of integrated IPs, which has resulted in a complex mix of centralized and distributed frequency dividers and clock controllers. In addition, there are many peripheral and system IPs or functions integrated in a SoC, each with its own internally divided clocks, so it is often difficult to implement an SoC with a duty cycle where 50% clock is required.

This article describes a new approach to implementing clock dividers in a system-on-chip design that supports both high performance and low power. It uses a dual edge counter-based configurable frequency divider that can not only divide the clock frequency for both even and odd configurable division factors, but at the same time maintains a 50% duty cycle of the output divided clock.

Maintaining a 50% duty cycle of the output clock for even division factors is not much of a challenge. But when it comes to odd division factors, extra design efforts are required. So by deployment of a dual edge counter, it is possible to build a configurable frequency divider with a 50% duty cycle of the output clock for both odd and even division factors.

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