20nm Dilemma Explained

Handel Jones, International Business Strategies Inc.
EETimes (4/4/2014 06:00 PM EDT)

Fully depleted silicon-on-insulator is the best solution for the 28nm and 20nm technology nodes because of its lower cost and leakage and higher performance than bulk CMOS.

The cost of a 100mm2 die in FD SOI at 28nm is 3.0% lower than bulk CMOS and 13.0% at 20nm due to higher parametric yield as well as lower wafer cost. The data also shows that an FD SOI die with comparable complexity to bulk CMOS is 10% to 12% smaller.

The combination of the smaller die area and higher parametric yield should give an equivalent product a 20% cost advantage at 20nm for FD SOI compared to bulk CMOS. In addition, at 28nm FD SOI has performance that is 15% higher than 20nm bulk CMOS. (See chart below.)

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