Leakage power optimization for 28nm and beyond

Aishwary Dadheech, Engineer, Dhaval Parikh, Senior Engineer, Jinesh Patel, Engineer, eInfochips
EDN (April 07, 2014)

As process nodes shrink towards nanotechnology, the supply voltage is scaled down to protect the device from excessive electric field across the gate oxide and the conducting channel. Another reason for supply voltage reduction is to save dynamic power dissipation. On the flip side, this voltage reduction slows down the CMOS transistor.

To overcome this performance loss, the transistors’ threshold voltage is decreased, which increases sub-threshold leakage current. At these nodes, leakage power can contribute more than 50% of the overall chip power – hence, high performance chips have excess power dissipation, even in standby mode. Increasing performance causes more leakage power dissipation.

To counter this challenge, the typical design flow uses positive slack margins of non-critical paths and adds cells with high Vt.

STA is pessimistic in physical design as it uses conservative timing calculations with Graph Based Analysis (GBA). Additional pessimism is introduced by flat OCV (On-Chip Variations) derating and heavy clock uncertainty. These are educated guesses derived from estimations of variations and tool correction errors respectively. But applying flat derates for all the standard cells globally also is not a realistic scenario because all cells cannot have the same (worst) variation.

The flow we’ve developed reduces pessimism and recommends three accurate and realistic timing approaches. We strive to increase the positive margin to maximize leakage power optimization – cells with positive slack get converted to HVT.

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