Rail analysis for SoC ASICs

Khalid Islam
EDN (May 26, 2014)

Rail analysis for an ASIC system on chip (SoC) falls into two broad categories, static and dynamic (also known as transient). Static analysis is driven by power consumption for the average situation, based on a switching probability for each instance in the design. This approach allows for the computation of IR drops and current densities to determine if the power and ground (PG) routing has a low enough resistance to deliver the required current for proper chip operation, and sufficient widths and via instantiations to carry the current without electromigration failure. Dynamic analysis, on the other hand, measures the transient droops or spikes in the voltage waveforms of the PG networks to determine whether the decoupling capacitance between the PG networks is sufficient to keep these deviations to an acceptable level, and to assess whether or not power up or power down operations satisfy the design specifications for power-managed designs. Both methods occupy an important place in the analysis of ASIC chips for predicting correct chip behavior in the field.

1 Rail Analysis Integration into Physical Design and Analysis Flows

In the realm of ASIC physical design (placement, routing, and circuit optimization), it is desirable to perform rail analysis as early as possible, to verify that the PG net routing that usually goes in as part of the floorplanning process is adequate, and will not have to be changed late in the flow. This early analysis is important, because placement and routing engines consider the routing resources that are left over after PG routing to be available for signal routing. So, late changes to PG routing can have a domino effect on the signal routing, and also on placement, as PG routing can effectively “block” legal placement locations, due to pin accessibility issues. In addition, the multi-patterning routing that is required at 20nm and below further complicates late changes to PG routing, as the available legal routing outcomes are more constrained and computationally much more intensive to achieve.

None of the foregoing precludes the need for sign-off or final stage rail analysis when the placement and routing have been completed, and the design is close to tape-out. Meeting the specified rail analysis targets at sign-off stage remains mandatory. What early flow rail analysis does, though, is limit sign-off stage surprises.

Click here to read more ...